The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and device for testing semiconductors. Merely by way of example, the invention has been applied to testing semiconductor degradation under certain stress. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single integrated circuit of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. One of the limitations in semiconductor manufacturing has been ensuring the reliability of semiconductors.
In the past, different types of testing methods and structures have been developed. Sometimes, package level reliability test, which requires dicing a wafer into pieces for the purpose of testing, is used. The process of dicing a wafer and testing pieces of semiconductor is often costly and slow. To speed things up, wafer level reliability test is sometimes used. During a wafer level reliability test, one or more test keys are often used. A test key, for example, is a circuit that is manufactured at the same time as the wafer under the same condition so that the reliability and performance of the wafer can be determined by the reliability and performance of test keys. Generally, test keys are placed at spare areas on a wafer or die. Unfortunately, abovementioned techniques for semiconductor testing are often inadequate. These and other limitations of the conventional techniques have been overcome, at least in part, by the invention that has been fully described below.
Therefore, it is desirable to have an improved method and system for a test structure on a wafer.